The present invention is related to a signal transmission device for minimizing simultaneous switching noise in integrated circuit chip (ICs), and in particular, to a signal transmission device which transmits n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in integrated circuit chip and the signal transmission method thereof.
In an integrated circuit chip, there is bound to proceed with a great deal of data transmissions and data processing tasks. With the increasing processing speed and data transmission rate and the decreasing rated working voltage for an integrated circuit, the inductance effect of the power/ground pads, especially wire-bond pads, in an integrated circuit chip is becoming more and more serious. FIG. 1(a) shows an equivalent circuit diagram in which a plurality of power pads 11 and ground pads 12 are used to interconnect an I/O driver including N I/O buffers 13 with a common power bus Vcc and a common ground bus GND, wherein the power pads 11 and the ground pads 12 are respectively represented by a parasitic inductor L1 and a parasitic inductor L2 as their parallel equivalent circuit elements, as shown in FIG. 1(b). Because the voltage VL1 across the inductors L1 and the voltage VL2 across the inductor L2 are directly proportional to the variation of the current flowing therethrough (V=Ldi/dt), while a large number of I/O buffers 13 are switching logic states simultaneously in the same direction, the variation of the current flowing through the inductors L1 or L2 will increase to cause the voltages VL1 or VL2 to increase, so that the voltage VN1 at node N1 or the voltage VN2 at node N2 will decrease as well. A surge of instantaneous current will be developed to flow through the I/O buffers 13, and thus power/ground noise will be generated in the power bus VCC and the ground bus GND. This noise is called simultaneous switching noise (SSN), commonly referred to as xe2x80x9cground/power bouncexe2x80x9d. The simultaneous switching noise is subject to deteriorate the signal transmission quality and lead the I/O buffers 13 to false switching operations. In view of the adverse effect of the simultaneous switching noise, how to minimize the simultaneous switching noise in an integrated circuit chip is a major object of the present invention.
A first respect of the present invention is directed to a signal transmission device for transmitting n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip. The signal transmission device according to a first respect of the present invention includes: an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (mxe2x88x92p), where Cpm greater than 2n and m greater than p greater than 0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals, so as to restore the n-bit parallel digital signals.
A second respect of the present invention is directed to a signal transmission device which transmits n-bit parallel digital signals through an I/O driver to reduce simultaneous switching noise in an integrated circuit chip. The signal transmission device according to a second respect of the present invention includes: an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at either p or p+1 and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at either (mxe2x88x92p) or (mxe2x88x92pxe2x88x921), where (Cpm+Cp+1m) greater than 2n and m greater than p+1 greater than p greater than 0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals, so as to restore the n-bit parallel digital signals.
A third respect of the present invention is directed to a signal transmission device which transmits n-bit parallel digital signals through an I/O driver to reduce simultaneous switching noise in an integrated circuit chip. The signal transmission device according to a third respect of the present invention includes: an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is limited within a range between p and (p+q) and the number of logic-0 bits of the encoded m-bit parallel digital signals is limited within a range between (mxe2x88x92pxe2x88x92q) and (mxe2x88x92p), where (Cpm+Cp+1m+Cp+2m+. . . +Cp+qm) greater than 2n and m greater than p+q greater than q greater than 0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals, so as to restore the n-bit parallel digital signals.
The I/O driver preferably includes m I/O buffers each shares a common power bus and a common ground bus, and is coupled with the common power bus and the common ground bus through power/ground pads. The encoding operation is performed by encoding each bit of the n-bit parallel digital signals one by one into the encoded m-bit parallel digital signals in conformity with the above-described rule, and the decoding operation is substantially an inverse of the encoding operation.
A fourth respect of the present invention is directed to a signal transmission method for transmitting n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip, including the following steps of: performing an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and a number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (mxe2x88x92p), where Cpm greater than 2n and m greater than p greater than 0, and performing a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.
A fifth respect of the present invention is directed to a signal transmission method for transmitting n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip, including the following steps of: performing an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at either p or p+1 and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at either (mxe2x88x92p) or (mxe2x88x92pxe2x88x921), where (Cpm+Cp+1m) greater than 2n and m greater than p+1 greater than p greater than 0, and performing a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.
A sixth respect of the present invention is directed to a signal transmission method for transmitting n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip, including the following steps of: performing an encoding operation to the n-bit parallel digital signals to provide an encoded m-bit parallel digital signals for the I/O driver, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is limited within a range between p and (p+q) and the number of logic-0 bits of the encoded m-bit parallel digital signals is limited within a range between (mxe2x88x92pxe2x88x92q) and (mxe2x88x92p), where (Cpm+Cp+1m+Cp+2m+. . . +Cp+qxe2x88x921m+Cp+qm) greater than 2n and m greater than p+q greater than q greater than 0, and performing a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.
According to a preferred embodiment of the present invention, the I/O driver is constituted by m I/O buffers each shares a common power bus and a common ground bus, and is coupled with the common power bus and the common ground bus through power/ground pads. The encoding operation is performed by encoding each bit of the n-bit parallel digital signals one by one into the encoded m-bit parallel digital signals in conformity with the above-described rule, and the decoding operation is substantially an inverse of the encoding operation.
A seventh respect of the present invention is directed to an integrated circuit chip having minimized simultaneous switching noise, including an internal circuit for generating n-bit parallel digital signals, an encoder coupled to the internal circuit for receiving the n-bit parallel digital signals and performing an encoding operation to the n-bit parallel digital signals to generate encoded m-bit parallel digital signals, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (mxe2x88x92p), where Cpm greater than 2n and m greater than p greater than 0, and m I/O pins coupled to the encoder for outputting the encoded m-bit parallel digital signals.
A eighth respect of the present invention is directed to an integrated circuit chip having minimized simultaneous switching noise, including an internal circuit for generating n-bit parallel digital signals, an encoder coupled to the internal circuit for receiving the n-bit parallel digital signals and performing an encoding operation to the n-bit parallel digital signals to generate encoded m-bit parallel digital signals, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at either p or p+1 and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at either (mxe2x88x92p) or (mxe2x88x92pxe2x88x921), where (Cpm+Cp+1m) greater than 2n and m greater than p+1 greater than p greater than 0, and m I/O pins coupled to the encoder for outputting the encoded m-bit parallel digital signals.
A ninth respect of the present invention is directed to an integrated circuit chip having minimized simultaneous switching noise, including an internal circuit for generating n-bit parallel digital signals, an encoder coupled to the internal circuit for receiving the n-bit parallel digital signals and performing an encoding operation to the n-bit parallel digital signals to generate encoded m-bit parallel digital signals, where m greater than n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is limited within a range between p and (p+q) and the number of logic-0 bits of the encoded m-bit parallel digital signals is limited within a range between (mxe2x88x92pxe2x88x92q) and (mxe2x88x92p), where (Cpm+Cp+1m+Cp+2m+. . . +Cp+qxe2x88x921m+Cp+qm) greater than 2n and m greater than p+q greater than q greater than 0, and m I/O pins coupled to the encoder for outputting the encoded m-bit parallel digital signals.
In accordance with a preferable implementation of the integrated circuit chip of the present invention, the I/O driver includes m I/O buffers each shares a common power bus and a common ground bus, and is coupled with the common power bus and the common ground bus through power/ground pads. In addition, the encoded m-bit parallel digital signals are transmitted to another one integrated circuit chip, including an I/O driver coupled to the m I/O pins for receiving the encoded m-bit parallel digital signals, a decoder coupled to the I/O driver for performing a decoding operation to the encoded m-bit parallel digital signals, so as to restore the n-bit parallel digital signals, and an internal circuit coupled to the decoder for processing with the n-bit parallel digital signals. Similarly, the I/O driver is constituted by m I/O buffers each shares a common power bus and a common ground bus, and is coupled with the common power bus and the common ground bus through wire-bond pads.
Now the foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the accompanying drawings, in which: